Voltage shift control circuit for PLL

ABSTRACT

A PLL comprises a PFD, a loop filter and a VCO, as well as a voltage shift capacitor coupling the PFD and the VCO. A voltage shift control circuit is placed in parallel with the voltage shift capacitor. This circuit comprises controlled charging means, which are designed to charge the voltage shift capacitor according to a channel control signal. It also comprises controlled pre-charging means which are designed to accelerate the charging of the voltage shift capacitor by the controlled charging means. It further comprises controlled biasing means, designed to ensure the bias of the input during the pre-charging of the voltage shift capacitor.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a voltage shift control circuitintended to be placed in parallel with at least one voltage shiftcapacitor coupling the phase or frequency comparator and the voltagecontrolled oscillator of a phase locked loop (PLL).

2. Related Art

PLLs have numerous uses in the electronics industry, among which is thegeneration of phase modulated or frequency modulated signals. Theapplications of the present invention are particularly intended for thisuse. In fact the invention can be applied in particular to theradio-frequency (RF) transmitters of fixed stations and of mobileterminals of digital radio-communications systems.

FIG. 1 illustrates the operating principle of a PLL. The PLL comprises aphase or frequency comparator (PFD) 10 which receives two input signals.The first one is a phase or frequency reference signal FREF and thesecond one is a signal FVCO coming from a voltage controlled oscillator(VCO) 30 and having undergone a frequency division in a variable ratiofrequency divider 40. The output voltage of the PFD is integrated by alow pass filter 20, called a loop filter. The output of the filtercontrols the VCO in such a way as to align the phases of the two inputsignals FREF and FVCO of the PFD. The VCO delivers the output signal ofthe PLL which oscillates about a reference frequency controlled andmodulated by the PLL.

It is possible to introduce frequency modulation (FM) at the level ofthe divider 40 by controlling the variable division ratio.

The performance characteristics of the PLL determine, in particular, thespectral purity of the output signal and the linearity of themodulation. In this respect, the absence of noise on the input of theVCO and the linearity of the gain of the PFD are of great importance.Embodiments of the PFD have been proposed which favour the linearity ofthe gain (see WO 97/01884). These embodiments necessitate that the DCcomponent of the output signal of the PFD should correspond with anoperating point substantially corresponding to the common mode (CM)voltage, that is to say to Vdd/2, where Vdd denotes the power supplyvoltage of the PLL.

In order to be able to change channels in the transmitter incorporatingthe PLL, means are provided for changing the DC component at the inputof the VCO. In fact, the mean frequency of the output signal variesaccording to the channel used, which means that the theoretical meanvoltage at the input of the VCO can vary from 0 to Vdd. The meansforming a voltage translator comprise, for example, a high valuecapacitor placed in series between the output of the PFD and the inputof the VCO.

Fast charging (or discharging) of this capacitor is desirable in orderto reduce the time lost when changing channels, in particular duringhandover operations of the mobile terminal comprising the PLL. Eventhough in the rest of this description reference is made only to thecharging of the capacitor, it is of course understood that this termrefers both to the capacitive charging and to the capacitive dischargingof this component, the capacitive charging being obtained by a positivecharging current and the capacitive discharging being obtained by anegative charging current.

BRIEF DESCRIPTION OF THE INVENTION

The purpose of the invention is to propose means for allowing a rapidcharging of the capacitive means forming a voltage translator, duringchanges of channel in the transmitter incorporating the PLL, whilstensuring good performance characteristics of the PLL in terms ofspectral purity and of linearity.

Thus purpose is achieved by means of a voltage shift control circuitintended to be placed in parallel with at least one voltage shiftcapacitor coupling the phase comparator and the voltage controlledoscillator of a phase locked loop. The circuit comprises:

-   -   an input, intended to be coupled with the output of the phase        comparator;    -   an output, intended to be coupled with the input of the voltage        controlled oscillator;    -   controlled charging means, designed to charge the voltage shift        capacitor according to a control signal;    -   controlled pre-charging means, designed to accelerate the        charging of the voltage shift capacitor by the controlled        charging means; and,    -   controlled polarization means, designed to ensure the        polarization of the input during the pre-charging of the voltage        shift capacitor.

A second aspect of the invention relates to a PLL comprising a phase orfrequency comparator, a loop filter, a voltage controlled oscillator, avoltage shift capacitor connecting the phase comparator and the voltagecontrolled oscillator, and a voltage shift control circuit such asdefined above, which is placed in parallel with the voltage shiftcapacitor.

A third aspect of the invention relates to a radio-frequencytransmitter, comprising a phase locked loop according to the secondaspect, for generating a radio-frequency signal to be transmitted.

A fourth and a fifth aspect of the invention further relate to a mobileterminal and to a base station respectively of a radio-communicationssystem comprising a radio-frequency transmitter according to the thirdaspect.

BRIEF DESCRIPTON OF THE DRAWINGS

FIG. 1 is a functional block diagram of a PLL;

FIG. 2 is a circuit diagram illustrating a first embodiment of a circuitaccording to the invention;

FIG. 3 is a graph showing an examplary response curve of a VCO;

FIG. 4 is a circuit diagram showing an example of a detailed embodimentof the pre-charging means of the circuit according to the invention;

FIG. 5 is a graph showing the input and output transient voltageresponses of the circuit according to the invention; and,

FIG. 6 is a circuit diagram showing a second embodiment of the circuitaccording to the invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

The present description provides example embodiments of a circuitaccording to the invention. The circuit can be produced in the form ofan ASIC (Application Specific Integrated Circuit) circuit, for exampleusing CMQS submicronic (0.35 μm or less) technology.

FIG. 2 is a circuit diagram which shows a first embodiment of thecircuit according to the invention.

The circuit 50 is powered via a high voltage power supply terminal Vddand a low voltage power supply terminal Vss. In one example, the lowvoltage power supply potential Vss is the ground potential and the highvoltage power supply potential Vdd, or power supply voltage, is equal to3.3 V.

The circuit comprises an input 21 and an output 22. The input 21 isintended to be coupled with the output of the PFD of a PLL and theoutput 22 is intended to be coupled with the input of the VCO of thePLL.

The function of the circuit 50 is, at the moment of channel change, topre-charge the input voltage of the VCO to a value close to the meanvalue corresponding to the chosen channel, whilst maintaining the outputvoltage of the PFD near the common mode voltage, that is to say Vdd/2,or 1.65 V in this example. Outside of the periods following a change ofchannel, the circuit 50 makes it possible to compensate for the currentlosses at the input of the VCO.

A capacitor Ca of high value, for example 1 μF, forming voltage shiftingmeans, is typically present between the input 21 and the output 22 ofthe circuit 50, being placed between the output of the PFD and the inputof the VCO of the PLL. This capacitor Ca can of course be replaced byany essentially capacitive structure, in particular by an assemblycomprising one or more capacitors connected in series and/or inparallel.

In FIG. 2, there is also shown an example of a loop filter 20 of thePLL. This filter 20 is a low-pass filter in this case comprising acapacitor C1 connected in parallel with an RC network, this latercomprising a resistor R2 in series with a capacitor C2, between theoutput 22 of the circuit and the Vss terminal. More particularly, thefilter 20 is placed in the PLL, between the output of the PFD and theinput of the VCO, downstream of the capacitor Ca. The invention is notof course limited to this example embodiment of the loop filter 20 andany low-pass filter structure may be suitable.

The other components of the PLL can comprise a variable ratio frequencydivider placed in the feedback path, as illustrated by the block diagramshown in FIG. 1.

Essentially, the circuit 50 comprises analogue means 51, 52 and 53, anda logic unit 54.

Controlled polarization means 53 are designed to ensure the polarizationof the input 21 during the pre-charging of the capacitor Ca, by imposingthe common mode voltage on that input. The means 53 can for examplecomprise an OTA (Operational Transconductance Amplifier) OTA2 connectedas a voltage follower. The non-inverting input of this operationalamplifier receives the common mode voltage generated by a resistivebridge comprising two identical resistors of high value connected inseries between the terminals Vdd and Vss. The inverting input of theoperational amplifier is connected to the input 21 through a controlswitch SW5. The switch SW5 is controlled by a control signal CTRL2generated by the logic unit 54.

In the activation of the polarization means configuration, that is tosay when the switch SW5 is closed, the operational amplifier OTA2imposes the common mode voltage on the terminal 21 of the circuit 50.That is why this amplifier is also called a common mode follower.

Controlled charging means 51, are designed to charge the capacitor Caaccording to a channel control signal received from outside of thecircuit. This channel control signal is for example coded in 8 bits. Itsfunction is to control the input voltage of the VCO at a value close tothe mean value (that is to say disregarding the modulation)corresponding to a chosen radio channel.

For this purpose, the means 51 comprise an operational transconductanceamplifier OTA1 connected as a voltage follower in parallel with thecapacitor Ca. They also comprise a controlled current source CSa whichsupplies a positive or negative current Ia through a resistor Ra placedin series in the feedback loop of the operational amplifier OTA1. Statedotherwise, the current source CSa is connected between the terminal Vssand the inverting input of the operational amplifier OTA1, this inputalso being looped to the output of this amplifier via the resistor Ra.The output of the operational amplifier OTA1 is connected to the output22 of the circuit through a resistor Rb of high value, for example 1 MΩ.The non-inverting input of the operational amplifier OTA1 is connectedto the input 21 of the circuit and also to the output of the operationalamplifier OTA2 of the means 53 via the switch SW5. Thus it receives thecommon mode voltage as a reference when this switch is closed by thesignal CTRL2, that is to say when the pre-charging is activated. In thisway, the charging of the capacitor Ca is carried out when there is achange of radio channel, at a voltage controlled by the aforesaidcontrol signal from the common mode voltage. This charging is thereforeoptimized in time.

The current source CSa is for example produced in the form of adigital-to-analogue converter supplying, in the case of a resistor Ra of33 kΩ, a current varying from −50 μA to +50 μA, by the intermediary ofthe control signal coded in 8 bits. Such a converter can advantageouslybe produced from 255 unit current sources. With regard to production onsilicon, these unit current sources are preferably mixed inside abarycentric matrix in order to limit current dispersions due to thermaleffects.

It will be noted that the noise of the operational amplifier OTA1, whenthe pre-charging is deactivated, is filtered by the components Rb, C1and C2 disposed downstream. This noise does not therefore affect theperformance characteristics of the PLL. This is an advantage incomparison with other possible structures, for which low noiseoperational amplifiers, occupying more space on silicon and consumingmore energy, are required.

The circuit 50 finally comprises controlled pre-charging means 52 whichare designed to accelerate the charging of the external capacitor Ca bythe controlled charging means 51 when there is a channel change. Themeans 52 comprise a push-pull stage formed from two transistors P3 andP4, which are a PMOS transistor and an NMOS transistor respectively,placed in series between the terminals Vdd and Vss. The control gates ofthe transistors P3 and P4 are connected to the control gates ofcorresponding transistors of a push-pull output stage of the operationalamplifier OTA1 (see FIG. 4, described later) through controlled switchesSW1 and. SW2 respectively. The output of the push-pull stage P3-P4 isconnected to the output 22 of the circuit. Thus connected, this stageshort-circuits the resistor Rb of high value when the switches SW1 andSW2 are closed. The closing of these switches is controlled by a controlsignal CTRL1 generated by the logic unit 54, when there is a change ofradio channel.

The functioning of the charging means 51 will now be described withreference to the diagram shown in FIG. 3. In this figure, a curve hasbeen shown which corresponds to a typical response curve of a VCO. Moreparticularly, the curve shows the trend of the frequency Fout of thesignal delivered on output from the VCO, as a function of the inputvoltage Vin of the VCO. In the applications of the invention that areenvisaged, the VCO must be able to deliver a radio-frequency signal in acontinuous band of width 50 MHz, ranging from about 380 MHz to about 430MHz, when the input voltage Vin varies between 1 V and Vdd. The VCO iscalibrated in such a way that the frequency Fout is situatedsubstantially in the centre of the abovementioned 50 MHz band when thevoltage Vin is substantially equal to the common mode voltage Vdd/2.

Let it be assumed that the chosen channel is situated at a frequencycorresponding to the point 31 on the curve. The means 51 must thengenerate a voltage shift represented by the interval 32 in the figure,with respect to the voltage Vdd/2. This shift is obtained by controllingthe current source CSa in such a way that it supplies a current suchthat the product Ra×Ia is equal to the voltage shift 32.

FIG. 4 shows in a detailed way the coupling of the pre-charging means 52with the operational amplifier OTA1. The latter is represented by thesymbol of a differential amplifier (i.e. a triangle) followed by apush-pull output stage composed of two transistors P1 and P2, that are aPMOS transistor and an NMOS transistor respectively, in series betweenthe terminals Vdd and Vss. The push-pull output stage P1-P2 is connectedto one end of the resistor Rb, the other end of which is connected tothe output of the push-pull stage P3-P4 of the means 52. The controlgates of the transistors P3 and P4 are connected to the control gates ofthe transistors P1 and P2 respectively by the intermediary of theaforementioned controlled switches SW1 and SW2.

When the signal CTRL1 is in a specified logic state, for example thelogic state 1, it thus causes the closing of the switches SW1, SW2, SW7and SW8. In this way the transistors P1 and P3, on the one hand, and thetransistors P2 and P4, on the other hand, become connected as a currentmirror. Furthermore, the resistor Rb is then short-circuited. It ispossible to provide a switch SW7 in parallel with the resistor Rb, theclosing of this switch being controlled by the signal CTRL1 when thepre-charging means 52 are activated, in such a way as to minimize theeffects of an unbalance between the push-pull P1-P2 and the push-pullP3-P4.

The transistors P3 and P4 preferably have a gate width substantiallygreater than that of the transistors P1 and P2 respectively and theydeliver a charging current for the capacitor Ca that is higher than thecurrent delivered by the transistors P1 and P2. For example, thetransistors P1 and P2 can be dimensioned such that they deliver acharging current of 100 μA and the transistors P3 and P4 can bedimensioned such that they deliver a current 20 times higher, that is tosay a current of 2 mA in this example. Stated otherwise, thepre-charging means 52 make it possible to accelerate the charging of thecapacitor Ca when they are activated by the signal CTRL1.

In an advantageous embodiment, switches SW3 and SW4 are also placedbetween the gate of the transistor P3 and the terminal Vdd and betweenthe gate of the transistor P4 and the terminal Vss respectively. Theseswitches SW3 and SW4 are controlled by a signal corresponding to theinverse of the control signal CTRL1. In this way, the switches SW3 andSW4 are closed when the pre-charging means 52 are deactivated, such thatthe transistors P3 and P4 are cut off. In this way the generation ofleakage currents through these transistors in the deactivated state ofthe means 52 is prevented.

Returning to FIG. 2, the functioning of, the pre-charging means 52 andof the polarization means 53 when there is a change of radio channelwill now be explained.

When there is a change of radio channel, the logic unit 54 sets thecontrol signal CTRL2 in such a way that it closes the switch SW5.Consequently, the common mode voltage Vdd/2 is imposed on the input 21of the circuit. It is also supplied as a reference to, the operationalamplifier OTA1 of the charging means 51.

Similarly, the logic unit 54 sets the control signal CTRL1 in such a waythat it closes the switches SW1 and SW2. The push-pull stage of thepre-charging means 52, of which the transistors P3 and P4 are connectedas a mirror of the corresponding transistors of the push-pull outputstage of the amplifier OTA1, then generates a high charging current,designed to accelerate the charging of the capacitor Ca in comparisonwith what it would be if only the charging means 51 were present.

It will be noted that the low output impedance of the operationalamplifier OTA2 operating as a common mode follower allows the evacuationof the charging current of the capacitor Ca.

After a given time, the logic unit 54 sets the control signals CTRL1 andCTRL2 in such a way as to deactivate the means 52 and 53 respectively.The output of the operational amplifier OTA2 is thus put into the highimpedance state, as are the control gates of the transistors P3 and P4of the pre-charging means 52. However, the means 51 remain active. Inthis way, possible current leakages at the input of the VCO arecompensated by the charging of the capacitor Ca by the means 51. Infact, the latter remain controlled by the channel control signal suchthat the current Ia continues to flow in the resistor Ra.

In FIG. 5, the curves 61 and 62 show the transient voltage response ofthe input of the VCO and of the output of the PFD of the PLLrespectively, following a change of radio channel occurring at the timet=0.

In the situation represented by the curve 61, the channel control signalcauses the mean input voltage of the VCO to change from 370 mV to 2.8 V.The pre-charging time, to within 1 mV of error, is of the order of 1 ms.

As shown by the curve 62, the output voltage of the PFD remainssubstantially constant during the pre-charging, at the common modevoltage (i.e. at 1.65 V).

Preferably, the polarization means 53 are deactivated after thepre-charging means 52. This makes it possible to reduce the injectionsof charge at the terminals of the voltage shift capacitor Ca. This isobtained by an appropriate time difference between the control signalsCTRL1 and CTRL2. This time difference is for example of the order of 1μs.

The circuit diagram shown in FIG. 6 illustrates another embodiment ofthe circuit according to the invention, which constitutes a refinementof the one shown in FIG. 2. In FIG. 6, the components that are the sameas those in FIG. 2 bear the same references and will not be describedagain.

As the loop filter 20 comprises an RC phase correction network formed bythe components R2 and C2, it has been observed that, when the currentsupplied by the PFD is low, the resistor R2 becomes effectively high andcan increase the pre-charging duration. It is therefore advantageous tohave a controlled current source for charging the capacitor C2.

In the illustrated embodiment, such a controlled current source 55comprises an additional push-pull stage P5-P6, connected as a mirrorwith the push-pull state P3-P4 of the pre-charging means 52 and withrespect to the push-pull output stage P1-P2 of the operational amplifierOTA1. More particularly, this additional push-pull stage comprises twotransistors P5 and P6, a PMOS transistor and an NMOS transistorrespectively, connected in series between the terminals Vdd and Vss, thegate of the transistor P5 being connected to the gate of the transistorP3 via a controlled switch SW5, and the gate of the transistor P6 beingconnected to the gate of the transistor P4 via another controlled switchSW6. The push-pull output stage P5-P6 is connected to the centre pointof the RC network, that is to say between the resistor R2 and thecapacitor C2, the former being connected between output 22 of thecircuit and said centre point and the latter being connected betweensaid centre point and the terminal Vss.

The closing, of the switches SW5 and SW6 is controlled by a controlsignal CTRL3 generated by the logic unit 54, independently from theactivation of the pre-charging means by the signal CTRL1. As a variant,it can be controlled by the signal CTRL1.

The additional push-pull stage P5-P6 can also be integrated in theoperational amplifier OTA1 of the pre-charging means 51.

1. Voltage shift control circuit intended to be placed in parallel withat least one voltage shift capacitor having a first terminal connectedto an output of the phase comparator and a second terminal connected toan input of the voltage controlled oscillator of a phase locked loop andcomprising: an input, intended to be coupled with the output of thephase comparator; an output, intended to be coupled with the input ofthe voltage controlled oscillator; controlled charging means, designedto charge the voltage shift capacitor according to a control signal;controlled pre-charging means, designed to accelerate the charging ofthe voltage shift capacitor by the controlled charging means; andcontrolled electrical polarization means, designed to ensure theelectrical polarization of the input during the pre-charging of thevoltage shift capacitor, wherein the charging means includes a firstoperational amplifier and the polarization means includes a secondoperational amplifier.
 2. Circuit according to claim 1, wherein thecontrolled charging means comprise the first operational amplifierconnected as a voltage follower between the input and the output, aresistor placed in the feedback loop of the operational amplifier, and acontrolled current source supplying a current of specified value throughsaid resistor.
 3. Circuit according to claim 2, wherein the operationalamplifier of the charging means comprise a push-pull output stage, andwherein the charging means further comprise a resistor of high valueconnected in series between the output of the operational amplifier andthe output of the circuit.
 4. Circuit according to claim 3, wherein thecontrolled pre-charging means comprise a push-pull stage which, in theactivation of the pre-charging means configuration, is arranged as amirror with respect to the push-pull output stage of the operationalamplifier of the charging means, in such a way as to short-circuit thehigh value resistor.
 5. Circuit according to claim 4, wherein thepush-pull stage of the pre-charging means is designed to deliver acurrent higher than the current delivered by the push-pull output stageof the operational amplifier of the charging means.
 6. Circuit accordingto claim 1, wherein the controlled polarization means comprise thesecond operational amplifier connected as a voltage follower which, inthe activation of the controlled polarization means configuration, isarranged to impose a common mode voltage on the input of the circuit. 7.Circuit according to claim 1, further comprising means for deactivatingthe controlled pre-charging means before the controlled polarizationmeans.
 8. Circuit according to claim 2, further comprising an additionalcontrolled push-pull stage whose output is intended to be connected tothe centre point of an RC network of a loop filter of the PLL and which,in the activation configuration, is connected as a mirror with respectto the push-pull stage of the controlled pre-charging means and withrespect to the push-pull output stage of the operational amplifier ofthe charging means.
 9. Circuit according to claim 8, wherein theadditional controlled push-pull stage is integrated with the operationalamplifier of the charging means.
 10. Circuit according to claim 1,designed in CMOS technology.
 11. Phase locked loop comprising a phase orfrequency comparator, a loop filter, a voltage controlled oscillator, avoltage shift capacitor coupled in series between the phase comparatorand the voltage control led oscillator, and a voltage shift controlcircuit according to claim 1 placed in parallel with the voltage shiftcapacitor and comprising: an input, intended to be coupled with theoutput of the phase comparator; an output, intended to be coupled withthe input of the voltage controlled oscillator; controlled chargingmeans, designed to charge the voltage shift capacitor according to acontrol signal and including a first operational amplifier; controlledpre-charging means, designed to accelerate the charging of the voltageshift capacitor by the controlled charging means; and controlledpolarization means, designed to ensure the polarization of the inputduring the pre-charging of the voltage shift capacitor and including asecond operational amplifier.
 12. Radio-frequency transmitter, having aphase locked loop for generating a radio-frequency signal to betransmitted, said phase locked loop comprising a phase or frequencycomparator, a loop filter, a voltage controlled oscillator, a voltageshift capacitor coupled in series between the phase comparator and thevoltage controlled oscillator, and a voltage shift control circuitaccording to claim 1 placed in parallel with the voltage shift capacitorand comprising: an input, intended to be coupled with the output of thephase comparator; an output, intended to be coupled with the input ofthe voltage controlled oscillator; controlled charging means, designedto charge the voltage shift capacitor according to a control signal andincluding a first operational amplifier; controlled pre-charging means,designed to accelerate the charging of the voltage shift capacitor bythe controlled charging means; and controlled polarization means,designed to ensure the polarization of the input during the pre-chargingof the voltage shift capacitor and including a second operationalamplifier.
 13. Mobile terminal of a radio-communications system with aradio-frequency transmitter having a phase locked loop for generating aradio-frequency signal to be transmitted, said phase locked loopcomprising a phase or frequency comparator, a loop filter, a voltagecontrolled oscillator, a voltage shift capacitor coupled in seriesbetween the phase comparator and the voltage controlled oscillator, anda voltage shift control circuit according to claim 1 placed in parallelwith the voltage shift capacitor and comprising: an input, intended tobe coupled with the output of the phase comparator; an output, intendedto be coupled with the input of the voltage controlled oscillator;controlled charging means, designed to charge the voltage shiftcapacitor according to a control signal and including a firstoperational amplifier; controlled pre-charging means, designed toaccelerate the charging of the voltage shift capacitor by the controlledcharging means; and controlled polarization means, designed to ensurethe polarization of the input during the pre-charging of the voltageshift capacitor and including a second operational amplifier.
 14. Basestation of a radio-communications system with a radio-frequencytransmitter having a phase locked loop for generating a radio-frequencysignal to be transmitted, said phase locked loop comprising a phase orfrequency comparator, a loop filter, a voltage controlled oscillator, avoltage shift capacitor coupled in series between the phase comparatorand the voltage controlled oscillator, and a series voltage shiftcontrol circuit according to claim 1 placed in parallel with the voltageshift capacitor and comprising: an input, intended to be coupled withthe output of the phase comparator; an output, intended to be coupledwith the input of the voltage controlled oscillator; controlled chargingmeans, designed to charge the voltage shift capacitor according to acontrol signal and including a first operational amplifier; controlledpre-charging means, designed to accelerate the charging of the voltageshift capacitor by the controlled charging means; and controlledpolarization means, designed to ensure the polarization of the inputduring the pre-charging of the voltage shift capacitor and including asecond operational amplifier.